Senior Dft Design Engineer

AMD AMD · Semiconductors · Bangalore, India · Engineering

This role is for a Senior DFT Design Engineer at AMD, focusing on Design-for-Test (DFT) and Design-for-Debug (DFD) features for ASIC design. The responsibilities include developing RTL for DFT features, performing DFT integration, synthesis, timing analysis, verification, and ATPG. The role also involves developing CAD software and scripts, and supporting pattern debug during silicon bring-up. While the company mentions AI and AMD's mission includes accelerating AI computing experiences, this specific role is in silicon design engineering for testability, not directly building AI models or systems.

What you'd actually do

  1. Develop RTL for ASIC design-for-test (DFT) features as per architectural or design flow automation specifications.
  2. Perform DFT RTL design integration, insertion, synthesis, equivalency checking, timing analysis and defining constraints, verification of DFx logic at RTL and GLS, ATPG and Scan GLS.
  3. Work with multi-functional teams and handling schedules
  4. Developing CAD software, scripts and other support technology to enable successful construction of DFT logics in complex SoC design.
  5. Performing scan insertion, ATPG verification and test pattern generation

Skills

Required

  • Verilog simulator
  • waveform debugging tools
  • debugging both RTL and gate level simulations
  • UNIX/Linux
  • scripting languages (e.g. TCL, c-shell, Perl)
  • Verilog design language
  • EDA tools/methodology
  • synthesis
  • equivalency checking
  • static timing analysis
  • CPU’s
  • memory
  • I/O controllers
  • problem-solving skills
  • communication skills

Nice to have

  • Knowledge of DFT techniques such as JTAG/IEEE standards, SSN, Scan and ATPG, memory BIST/repair or Logic BIST
  • Expertise in scan compression architecture, scan insertion and ATPG methodologies are essential.
  • Working knowledge and experience in Verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations
  • Good working knowledge of UNIX/Linux and scripting languages (e.g. TCL, c-shell, Perl)
  • Familiar with Verilog design language, Verilog simulator and waveform debugging tools
  • Knowledge of EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis is a plus.
  • Understanding various technologies that must work with DFT/DFD technology such as CPU’s, memory and I/O controllers, etc. is a plus

What the JD emphasized

  • DFT RTL design integration
  • Scan insertion
  • ATPG verification
  • test pattern generation
  • DFT feature bring-up
  • pattern debug support
  • first silicon bring-up
  • qualification
  • failure analysis
  • scan compression architecture
  • scan insertion
  • ATPG methodologies