Senior Dft Engineer

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA

Senior DFT Engineer role at NVIDIA focusing on optimizing design tradeoffs and methodology for next-generation CMOS technology. Responsibilities include all aspects of testing: methodology, logic insertion, verification, test pattern generation, test program bring-up, and debug/failure analysis. Requires 12+ years of experience in design for test, knowledge of various test architectures, expertise in test logic design verification and pattern generation, and ATE test program development.

What you'd actually do

  1. You will be responsible for all aspects of testing including methodology, logic insertion, verification, test pattern generation, test program bring-up, and complex debug/FA to resolve any issues.
  2. Finding the right tradeoffs between test time and the ability to collect necessary data to monitor the health of next generation process nodes.
  3. Work as part of the team to design and tapeout advanced packaging vehicles.
  4. Assist with finding the root cause of product bring-up testing issues

Skills

Required

  • BS in Electrical or Computer Engineering or equivalent experience
  • 12+ years experience in design for test
  • In-depth knowledge of various test architectures including IEEE1149.1, IEEE1500, SSN scan compression, IOBIST, and memory BIST.
  • Expertise in test logic design verification and pattern generation.
  • Experience in doing ATE test program development and bring-up including spec'ing custom test methods needed for data collection.
  • Hands-on knowledge of industry standard DFT EDA tools.
  • Proficiency in programming and scripting languages, such as Python.

Nice to have

  • Experience with DDR and HBM high speed I/O testing.
  • Hands on experience with failure analysis equipment like LVP, photon emission, and ebeam probing.
  • Proficiency with Advantest 93k testers.

What the JD emphasized

  • 12+ years experience in design for test
  • In-depth knowledge of various test architectures including IEEE1149.1, IEEE1500, SSN scan compression, IOBIST, and memory BIST.
  • Expertise in test logic design verification and pattern generation.