Senior Dft Engineer

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA

Senior DFT Engineer role at NVIDIA, focusing on designing and verifying test access mechanisms, IO BIST, memory BIST, and scan compression for complex semiconductor chips. The role involves developing DFT methodologies, mentoring junior engineers, and collaborating with cross-functional teams. Requires expertise in scan test plans, BIST, fault modeling, ATPG, fault simulation, silicon debug, and scripting skills.

What you'd actually do

  1. As a member in our team, you will own and work with cross functional teams, implementing state-of-the-art designs in test access mechanisms, IO BIST, memory BIST and scan compression.
  2. In addition, you will help develop and deploy DFT methodologies for our next generation products.
  3. You will also help mentor junior engineers on test designs and trade-offs including cost and quality.

Skills

Required

  • BSEE or equivalent experience
  • MSEE or equivalent experience
  • PhD or equivalent experience
  • DFT
  • scan test plans
  • BIST
  • memory BIST
  • IO BIST
  • fault modeling
  • ATPG
  • fault simulation
  • verification
  • validation
  • RTL design
  • clocks design
  • STA
  • place-n-route
  • power analysis
  • Silicon debug
  • ATE
  • pattern formats
  • failure processing
  • test program development
  • Perl
  • Python
  • Tcl
  • analytical skills
  • communication skills

Nice to have

  • cross functional collaboration
  • mentoring junior engineers

What the JD emphasized

  • 8+, MSEE with 5+ years of experience or PhD with 3+yrs in DFT or related domains
  • Demonstrated knowledge and expertise in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG and fault simulation
  • Experience in Silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development