Senior Dft Engineer

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA

NVIDIA is seeking a Senior DFT Engineer to work on groundbreaking innovations in DFT architecture, verification, and post-silicon validation for complex semiconductor chips. The role involves implementing state-of-the-art designs in test access mechanisms, IO BIST, memory BIST, and scan compression, as well as developing and deploying DFT methodologies for next-generation products. The engineer will also mentor junior team members.

What you'd actually do

  1. As a member in our team, you will own and work with cross functional teams, implementing state-of-the-art designs in test access mechanisms, IO BIST, memory BIST and scan compression.
  2. In addition, you will help develop and deploy DFT methodologies for our next generation products.
  3. You will also help mentor junior engineers on test designs and trade-offs including cost and quality.

Skills

Required

  • BSEE (or equivalent experience) with 5+, MSEE with 3+ years of experience or PhD in DFT or related domains
  • Demonstrated knowledge and expertise in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG and fault simulation
  • Excellent analytical skills in verification and validation of test patterns and logic on complex and multi-million gate designs using vendor tools
  • Good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs
  • Experience in Silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development
  • Strong programming and scripting skills in Perl, Python or Tcl
  • Extraordinary written and oral communication skills

Nice to have

  • curiosity to work on rare challenges

What the JD emphasized

  • state-of-the-art designs
  • next generation products
  • complex semiconductor chips