Senior Dfx Power Methodology Engineer

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA

This role focuses on Design-for-X (DFX) for power, thermal, and voltage noise methodology in semiconductor chip design, specifically for datacenter GPUs. It involves innovating low power and thermal solutions for manufacturing tests, analyzing post-silicon data for power, and developing/deploying DFT methodologies using Applied ML & Gen AI solutions. The role also includes mentoring junior engineers and requires strong programming skills for AI coding harnesses.

What you'd actually do

  1. As a senior member in our team, you will work on innovating in the DFX Power, Thermal & Voltage Noise Methodology areas.
  2. This will include working on groundbreaking low power & thermal solutions for our manufacturing tests to be enabled at conditions that push the boundaries for our datacenter GPUs.
  3. You will work with multi-functional teams including Product Development & Power Architecture, implementing brand-new methodologies on hard-to-solve problems for improving our outgoing quality of chips.
  4. You will work on post-silicon data analysis for power to architect the next-gen solutions.
  5. In addition, you will help develop and deploy DFT methodologies for our next generation products using Applied ML & Gen AI solutions.

Skills

Required

  • BSEE (or equivalent experience) with 12+, MSEE with 10+, or PhD with 6+ years of experience in DFT design & power
  • Understanding of fundamental DFT topics and VLSI areas of power, timing & voltage noise
  • Excellent knowledge in using statistical tools for data analysis & insights.
  • Good exposure to multi-functional areas including RTL & clocks design, STA, place-n-route and power.
  • Experience in Silicon debug and bring-up on the ATE or SLT platforms.
  • Be able to think like a programmer so that this can be translated into action using AI Coding harnesses
  • Outstanding written and oral communication skills

Nice to have

  • Experience in Power Analysis, Thermal Analysis & IR Drop tools is a plus.
  • Experience in application of AI for EDA-related problem-solving is a plus.
  • Experience in managing DFT Power Methodology for designs
  • Experience in post-silicon debug for thermal & IR Drop

What the JD emphasized

  • hard-to-solve problems
  • Applied ML & Gen AI solutions
  • AI for Chip Design
  • AI for Predictions

Other signals

  • Applied ML & Gen AI solutions
  • AI for Chip Design
  • AI for Predictions