Senior Digital Design Verification Engineer - Hardware

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA

Senior Digital Design Verification Engineer at NVIDIA to verify SerDes IPs using UVM, SystemVerilog, and coverage-driven methodologies. Requires 5+ years of experience, strong verification background, and expertise in simulation/debug tools. Experience with bus protocols, mixed-signal designs, and programming languages like Python is a plus.

What you'd actually do

  1. Verification of the digital design, golden models and micro-architecture of the SerDes IPs using advanced verification methodologies such as UVM.
  2. Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.
  3. Responsible for understanding the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.
  4. Write and implement test plan and thoroughly verify a design in a product shipment focused / compressed schedule.
  5. Work with architects, designers, and pre and post silicon verification teams to accomplish your tasks.

Skills

Required

  • Bachelors or Masters Degree in Electrical Engineering, Computer Science, or Computer Engineering
  • 5 years of validated experience
  • SystemVerilog
  • random stimulus
  • functional coverage
  • assertion-based verification methodologies
  • UVM/VMM
  • industry standard verification tools for simulation and debug

Nice to have

  • bus or interconnect protocols (e.g. PCI Express, USB, SATA)
  • verifying complex SerDes system
  • understanding mixed-signal designs
  • modeling of analog circuits
  • Perl
  • Python
  • C/C++ programming language
  • debugging and analytical skills
  • interpersonal skills
  • teamwork

What the JD emphasized

  • SystemVerilog a must
  • functional coverage and assertion-based verification methodologies a must