Senior Digital Design Verification Engineer - Hardware

NVIDIA NVIDIA · Semiconductors · Hsinchu, Taiwan +1

Senior Digital Design Verification Engineer at NVIDIA, focusing on SerDes IPs that enable AI, deep learning, and autonomous driving. Responsibilities include verifying digital designs, building verification infrastructure, and working with cross-functional teams using UVM and SystemVerilog.

What you'd actually do

  1. Verification of the digital design, golden models and micro-architecture of the SerDes IPs using advanced verification methodologies such as UVM.
  2. Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.
  3. Responsible for understanding the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.
  4. Write and execute test plan and thoroughly verify a design in a product shipment focused / compressed schedule.
  5. Work with architects, designers, and pre and post silicon verification teams to accomplish your tasks.

Skills

Required

  • Bachelors or Masters Degree (or equivalent experience) in Electrical Engineering, Computer Science, or Computer Engineering
  • At least 5 years of proven experience
  • Background in verification at Unit/Sub-system/SOC level
  • SystemVerilog
  • Experience using random stimulus along with functional coverage and assertion-based verification methodologies
  • Experience in verification methodologies like UVM/VMM
  • exposure to industry standard verification tools for simulation and debug

Nice to have

  • Expertise in bus or interconnect protocols (e.g. PCI Express, USB, SATA)
  • Experience in verifying complex SerDes system, understanding mixed-signal designs, and have experience in modeling of analog circuits
  • Perl, Python, C/C++ programming language experience
  • Good debugging and analytical skills
  • Good communication skills & dream to work as a great teammate

What the JD emphasized

  • SystemVerilog a must
  • random stimulus along with functional coverage and assertion-based verification methodologies a must