Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will be responsible for turning communication theory into efficient, bit-exact silicon logic. You will take high-level models and transform them into the high-speed DSP blocks that anchor our next-gen architecture.
The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
- Design and implement DSP algorithms for high-speed PHYs, focusing on feed-forward equalization (FFE)/decision feedback equalization (DFE) and timing recovery loops.
- Perform fixed-point analysis to minimize bit-width (area/power) while maintaining the required signal-to-noise ratio (SNR).
- Develop bit-exact C++/SystemC models to verify register-transfer level (RTL) against architectural intent.
Qualifications
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field or equivalent practical experience.
- 8 years of experience in digital signal processing (DSP) design or high-speed digital logic design.
- Experience implementing digital blocks for communication systems or physical layer (PHY) architectures (e.g., filters, interpolators, or timing recovery).
- Experience in MATLAB, Python, or C++ for algorithm modeling and fixed-point analysis.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related technical field or equivalent practical experience.
- Experience with fin field-effect transistor (FinFET) process nodes (5nm, 3nm) and timing closure at GHz frequencies.
- Experience with universal verification methodology (UVM) verification environments.