Senior Formal Verification Engineer – AI Soc Development

Intel Intel · Semiconductors · California, Folsom, United States +3

This role focuses on ensuring the functional correctness of complex digital designs for AI SoCs using formal methods. The engineer will own the formal verification strategy, develop environments, write properties, collaborate with design teams, and contribute to pre-silicon verification and post-silicon debug. The role also involves defining verification plans, executing them using simulation and emulation, debugging issues, and incorporating security verification activities.

What you'd actually do

  1. Own formal verification strategy and execution for complex SoC IP blocks and subsystems.
  2. Develop and maintain formal verification environments using SystemVerilog Assertions (SVA) and industry-standard formal tools.
  3. Write and review formal properties, constraints, and coverage goals to achieve exhaustive verification.
  4. Collaborate with design and simulation teams to identify corner cases and complement dynamic verification.
  5. Drive formal sign-off, including convergence analysis and coverage closure.

Skills

Required

  • ASIC/SoC verification
  • formal verification
  • SystemVerilog Assertions (SVA)
  • formal verification tools
  • digital design concepts
  • clock domain crossings
  • low-power design techniques
  • scripting skills (Python, TCL, Perl)

Nice to have

  • UVM-based simulation environments
  • security verification

What the JD emphasized

  • security verification activities