Senior Front End Design Engineer (microarchitecture)

Cerebras Cerebras · Semiconductors · India · Silicon

Senior Front End Design Engineer (Microarchitecture) at Cerebras Systems, focusing on designing and developing the next generations of their AI chip, the Wafer Scale Engine (WSE). Responsibilities include RTL design, integration, and collaborating with various teams to bring semiconductor architectures from concept to production. Requires 8+ years of experience in complex RTL designs and a background in networking, HPC, or machine learning fields.

What you'd actually do

  1. Drive all aspects of chip design, including Functional Specification, Micro-architecture, RTL development, Synthesis.
  2. Work closely with PD team members for design closure to meet PPA goals.
  3. Work closely with Design verification and DFT teams for achieving the best functional and test coverage.
  4. Work with software and system teams to understand opportunities to deliver optimal performance and feature set for the product.
  5. Debug silicon-level functional, timing, and power issues during bring up.

Skills

Required

  • RTL design
  • Chip integration
  • Functional Specification
  • Micro-architecture
  • Synthesis
  • PPA goals
  • Design verification
  • DFT
  • Silicon bring up
  • Networking
  • High-performance computing
  • Machine learning
  • TCP/IP
  • RDMA
  • Ethernet
  • PCIe
  • CPU interfaces
  • Serdes technology
  • Python
  • TCL

Nice to have

  • FPGA development toolchain
  • Place and Route
  • Floor planning
  • Timing Analysis
  • ASIC vendor management

What the JD emphasized

  • 8+ years of experience in delivering complex, high performance high quality RTL designs
  • Proven track record of multiple silicon success