Senior Front End Design Engineer (microarchitecture)

Cerebras Cerebras · Semiconductors · Headquarters +1 · Silicon

This role is for a Senior Front End Design Engineer focused on the microarchitecture of Cerebras' AI chips. While the company builds hardware for AI, the role itself is in semiconductor design (RTL, synthesis, PPA, etc.) and not directly involved in building AI models or systems. The responsibilities are centered on chip design and integration, with a focus on performance and power efficiency for AI compute.

What you'd actually do

  1. Drive all aspects of chip design, including Functional Specification, Micro-architecture, RTL development, Synthesis.
  2. Work closely with PD team members for design closure to meet PPA goals.
  3. Work closely with Design verification and DFT teams for achieving the best functional and test coverage.
  4. Work with software and system teams to understand opportunities to deliver optimal performance and feature set for the product.
  5. Debug silicon-level functional, timing, and power issues during bring up.

Skills

Required

  • RTL design
  • Chip integration
  • Functional Specification
  • Micro-architecture
  • Synthesis
  • PPA goals
  • Design verification
  • DFT
  • Silicon bring up
  • Networking stack
  • TCP/IP
  • RDMA
  • Ethernet
  • PCIe
  • CPU interfaces
  • Serdes technology
  • Python
  • TCL

Nice to have

  • FPGA development toolchain
  • Place and Route
  • Floor planning
  • Timing Analysis
  • Managing external ASIC vendor

What the JD emphasized

  • 8+ years of experience in delivering complex, high performance high quality RTL designs
  • Proven track record of multiple silicon success