Senior Full Chip Layout and Physical Verification Cad Engineer

NVIDIA NVIDIA · Semiconductors · Yokneam, Israel +1

NVIDIA is seeking a Senior Full Chip Layout and Physical Verification CAD Engineer to join their Networking Silicon engineering team. The role involves developing full-chip physical design methodologies, physical verification, and tapeout activities for networking chips and SOCs. Responsibilities include working with layout owners, developing unique solutions for physical design problems, and running/debugging physical verification flows. Requires B.SC./M.SC. in Electrical/Computer Engineering or equivalent, 5+ years of experience in full-chip layout and physical verification, strong background in DRC/LVS/ANT/ERC/DFM, proficiency in Python, Tcl, Shell, Make scripting, and Linux environments. Familiarity with EDA tools like Synopsys and Cadence, and physical verification tools like Synopsys ICV and Siemens Calibre is necessary. Experience with data collection/analysis and methodology definition is a plus. AI tools orientation or a desire to learn is mentioned.

What you'd actually do

  1. You will be in charge of developing full-chip physical design methodologies, Physical Verification development and support through all the projects, Tapeout activities for implementation of networking chips and SOCs.
  2. Work closely with Full Chip Layout owners and block owners, project managers to assure high quality and timely convergence.
  3. Come up with unique and creative solutions to the state of the art FCL physical design problems that are needed for our chips.
  4. We expect you to run, debug, and approve Physical Verification flows across multiple projects, ensuring strict adherence to our high standards.
  5. Participating and developing flow and tool methodologies for fullchip, physical design verification across multiple projects.

Skills

Required

  • B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience)
  • 5+ years of hands-on Full-chip layout and Physical Verification experience
  • Strong background in Physical Verification methodology, including DRC / LVS / ANT / ERC / DFM in advanced process nodes
  • Proficiency using Python, Tcl, Shell, Make scripting
  • Experience in Linux environments
  • Familiarity with physical build EDA tools, including Synopsys (ICC2/FC) and Cadence (Innovus)
  • Familiarity with Physical Verification tools: Synopsys (ICV), Siemens (Calibre)

Nice to have

  • Experience with data collection and analysis
  • Experience in methodology definition / flow owner of Full-chip / Place and Route
  • AI tools orientation or alternatively a desire to learn

What the JD emphasized

  • at least 5+ years of hands-on Full-chip layout and Physical Verification experience
  • A strong background in Physical Verification methodology, including DRC / LVS / ANT / ERC / DFM in advanced process nodes is necessary.