Senior Hardware Soc Architect

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA +2

NVIDIA is seeking a Senior Hardware SoC Architect to define next-generation SoCs for accelerating machine learning, automotive, and high-performance computing applications. The role involves defining clock and reset architecture, developing C-models, and collaborating with various engineering teams. Requires strong knowledge of clock generation, distribution, computer architecture, ASIC design flows, and SystemC/scripting.

What you'd actually do

  1. define clock and reset architecture, based on IP and product requirements
  2. capture these requirements in various architecture documents clearly and drive their reviews
  3. develop and improve architectural C-models and support the teams that use them
  4. review both upstream and downstream specifications and verification plans
  5. implementing methodologies that would help improve the efficiency of the team and the quality of our outputs

Skills

Required

  • BS/MS in EE/CE (or equivalent experience) plus 3+ years of industry experience
  • Deep knowledge of clock generation, distribution and microarchitecture
  • Good understanding of Computer Architecture
  • Firsthand knowledge of ASIC design/verification/implementation flows
  • Strong C++/SystemC experience
  • Excellent written, verbal and negotiation skills
  • Expert analytical and independent problem-solving skills
  • Strong scripting skills in languages such as Perl or Python
  • Experience with Architectural Methodology, Flows and processes

Nice to have

  • Experience with Clock and Reset Architecture Definition or Architectural C-Models
  • Detailed knowledge of one or more of: 1) PLLs, DLLs, etc, 2) clock-related signal integrity effects, or 3) platform power and reset sequencing
  • First hand work experience with reset generation and distribution
  • Automotive Functional Safety working experience with ISO26262 standard

What the JD emphasized

  • define future aspects of our architectures
  • pushing the state of the art
  • Clock and Reset Architecture Team
  • interest in clocks, resets and power management for SOCs
  • strong background in System C-modeling and scripting
  • improving methodologies and automations for improving team efficiency
  • Deep knowledge of clock generation, distribution and microarchitecture
  • Firsthand knowledge of ASIC design/verification/implementation flows
  • Strong C++/SystemC experience
  • Expert analytical and independent problem-solving skills
  • Experience with Architectural Methodology, Flows and processes
  • Experience with Clock and Reset Architecture Definition or Architectural C-Models
  • Detailed knowledge of one or more of: 1) PLLs, DLLs, etc, 2) clock-related signal integrity effects, or 3) platform power and reset sequencing
  • First hand work experience with reset generation and distribution