Senior Hardware Validation Methodology Engineer

NVIDIA NVIDIA · Semiconductors · Shanghai, China

NVIDIA is looking for a Senior Hardware Validation Methodology Engineer to define and own the methodology for validation platforms, ensuring compatibility and driving alignment between silicon validation and platform design teams. The role involves creating requirements, maintaining documentation, and collaborating with cross-functional teams across various programs.

What you'd actually do

  1. Create and own methodology for deriving baseline requirements for validation platforms.
  2. Collaborate with cross‑functional silicon validation teams to understand justification, tradeoffs, and design constraints, and reflect them in platform requirements.
  3. Ensure the bring‑up platform is fully compatible with required thermal solutions, power‑delivery configurations, and platform peripherals.
  4. Maintain the Engineering Requirements Document (ERD) to capture and track validation platform requirements across datacenter, client, automotive, and embedded programs.
  5. Primary interface between silicon validation teams and platform design teams, driving alignment on requirements and final implementation.

Skills

Required

  • BS or MS degree in EE/CE or equivalent experience
  • Effective in a collaborative environment
  • 5+ years of experience in silicon bring-up, platform validation, and platform design
  • Working experience in HSIOs like PCIE or chip-to-chip interconnects including understanding of process/temp/voltage sensitivity on BER
  • Broad exposure to various silicon validation and bring-up stages, including system integration testing, speed characterization, noise characterization, feature tuning, electrical validation, thermal and power controller tuning, PVT testing, HTOL, and SLT
  • Experienced in PCB design and/or layout as well as familiar with large-scale data center topologies involving hosts, switches, retimers, and end points
  • Strong foundation in electrical engineering, with solid knowledge of computer architecture, high-speed interfaces, timing analysis, process variations, statistical error rates, and power analysis

Nice to have

  • Experience in applying AI to semiconductor co-design/validation problems
  • Knowledgeable in using AI-assisted workflows to accelerate automation, data analysis, root cause investigation, and documentation

What the JD emphasized

  • 5+ years of experience in silicon bring-up, platform validation, and platform design.
  • Experience in applying AI to semiconductor co-design/validation problems and learning the domain quickly.
  • Knowledgeable in using AI-assisted workflows to accelerate automation, data analysis, root cause investigation, and documentation.