Senior Hsio Validation Engineer

NVIDIA NVIDIA · Semiconductors · Taipei, Taiwan

NVIDIA is seeking a Senior HSIO Validation Engineer to architect and build system and platform level features for silicon validation. This role involves collaborating with various teams, defining roadmaps, supporting silicon bring-up, and coordinating the implementation of interfaces for GPUs, SOCs, and CPUs. The ideal candidate will have a strong understanding of PCIe protocols, signal integrity, and hands-on experience with lab equipment and scripting for validation.

What you'd actually do

  1. Innovate and Build: Architect and build system and platform level features to improve power, performance, quality, and manufacturability. Develop innovative methods to improve the silicon validation process, ensuring we meet the highest industry standards.
  2. Collaborate and Lead: Work closely with ASIC, VLSI, SW, board design, SLT/ATE, and AE teams throughout the product lifecycle. Lead platform-related development, optimization, productization, debugging, and deployment efforts.
  3. Push the Boundary: Define roadmaps based on market trends, collect product feedback, prototype new insights, and conduct data-driven tradeoff analysis.
  4. Hands-on Actions: Support silicon bring-up, validation, and debugging; coordinate product-level feature deployment; lead efforts to address customer issues.
  5. Drive Planning and Execution: Coordinate the planning and implementation of NVLINK/C2C or similar interfaces in functional bring-up, system-level validation, productization, and issue resolution for NVIDIA GPUs, SOCs, and CPUs.

Skills

Required

  • BS or MS in Electrical/Computer Engineering or equivalent experience
  • 5 years of relevant experience
  • PCIe protocol and characterization/validation methods
  • Signal integrity concepts
  • Silicon characteristics
  • High-speed/SERDES functional validation
  • Lab equipment (DSOs, BERT, protocol/logic analyzers)
  • Hands-on post-Si bring-up and functional validation of HSIO interfaces
  • Scripting skills in Perl and Python

Nice to have

  • NVLINK/C2C interface experience

What the JD emphasized

  • minimum of 5 years of relevant experience
  • In-depth understanding of PCIe (or similar) protocol and characterization/validation methods in a post-silicon environment
  • Excellent knowledge of signal integrity concepts, silicon characteristics, and high-speed/SERDES functional validation
  • Proficiency with lab equipment (DSOs, BERT, protocol/logic analyzers) and hands-on post-Si bring-up and functional validation of HSIO interfaces
  • Strong scripting skills in languages such as Perl and Python for writing test/debug programs for stress and failure analysis