Senior I/o Subsystem Architect

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA

This role focuses on defining and architecting advanced chip interconnects and protocols, specifically for NVLink chip-to-chip communication. The responsibilities include researching and crafting architecture solutions, collaborating with various design and software teams, and driving the product lifecycle from concept through deployment. The role requires extensive experience in link layer architecture and existing interconnects.

What you'd actually do

  1. Researching and crafting architecture solutions for chip-to-chip communication, optimizing for performance, area, power, security, and resiliency
  2. Working with other design teams to define interfaces and flows between NVLink C2C blocks and the rest of the chip
  3. Architectural modeling, validation, definition and documentation
  4. Driving implementation across design, verification, firmware and software teams
  5. Working with various teams to define NVLink C2C architecture

Skills

Required

  • MS or PhD in Electrical Engineering, Computer Science or Computer Engineering (or equivalent experience)
  • 10+ years of relevant experience in some combination of architecture, design, and verification
  • Proven experience over link layer architecture (Transaction layer, Data link layer, Physical layer)
  • Experience with existing interconnects (PCIE, UCIE, Chip to Chip links)
  • Knowledge of Industry standard protocols CHI/CXL/AXI
  • Ability to define system architecture with NVLINK-C2C interconnects and SW stack around it
  • Collaboration with multi-functional teams
  • Evaluate and trade off technical solutions
  • Completed and shipped multiple projects
  • Skilled at I/O Architecture
  • Experience leading projects from concept through product lifecycle

What the JD emphasized

  • 10+ years of relevant experience in some combination of architecture, design, and verification
  • Proven experience over link layer architecture (Transaction layer, Data link layer, Physical layer)
  • Experience with existing interconnects (PCIE, UCIE, Chip to Chip links) and knowledge of Industry standard protocols CHI/CXL/AXI
  • Have completed and shipped multiple projects and are skilled at I/O Architecture
  • Experience leading projects from concept through product lifecycle, including pathfinding, prototyping, and deployment