Senior Implementation Methodology Engineer

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA +1

This role focuses on the front-end design implementation methodologies, flow automation, and application support for NVIDIA's critical designs, aiming to improve power, performance, and area. It involves collaboration with logic designers, physical designers, and EDA vendors, as well as providing support for EDA tools and flows. The position requires a BS or MS in Electrical Engineering, Computer Engineering, or related fields with 8+ years of experience in logic or physical design implementation, a deep understanding of logic optimization, physical design implementation, and proficiency in synthesis and place and route EDA tools.

What you'd actually do

  1. You will be responsible for all aspects of front-end design implementation methodologies (synthesis, formal-equivalence-checking), flow automation and application support.
  2. Use NVIDIA implementation flows and EDA tool expertise to improve power, performance and area on NVIDIA's most critical designs
  3. You will collaborate with logic designers, physical designers and EDA vendors to solve exciting implementation issues and develop new solutions.
  4. Provide support for EDA tools and flows

Skills

Required

  • BS or MS in Electrical Engineering, Computer Engineering, or related fields (or equivalent experience)
  • 8+ years of experience in logic design implementation and/or physical design implementation
  • Deep understanding of logic optimization techniques and relative area, timing, and power trade-offs
  • Strong understanding of physical design implementation eg: physical synthesis, placement, routing, logic restructuring, etc.
  • Power user of synthesis and/or place and route EDA tools from Synopsys (DC/FC), Cadence (Genus/Innovus)
  • Good debugging and problem-solving skills
  • Strong interpersonal skills

Nice to have

  • Prior experience in physical implementation
  • Proficiency in Perl, Python, Tcl, Make scripting

What the JD emphasized

  • 8+ years of experience in logic design implementation and/or physical design implementation
  • Deep understanding of logic optimization techniques and relative area, timing, and power trade-offs
  • Strong understanding of physical design implementation eg: physical synthesis, placement, routing, logic restructuring, etc.
  • Should be a power user of synthesis and/or place and route EDA tools from Synopsys (DC/FC), Cadence (Genus/Innovus)