Senior Ip Dv Engineer - Noc Ip

NVIDIA NVIDIA · Semiconductors · Bangalore, India

Senior Verification Engineer to verify the design and implementation of memory subsystem units for GPUs and SOCs, impacting product lines from consumer graphics to self-driving cars and AI. Responsibilities include defining verification scope, developing infrastructure, and ensuring correctness using advanced methodologies like SV/UVM.

What you'd actually do

  1. You will be responsible for verifying the ASIC design, architecture and micro-architecture of memory sub-systems/units using advanced verification methodologies.
  2. Understand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.
  3. Coming up come up with test plans, tests and verification infrastructure for complex IPs/sub-systems.
  4. Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.
  5. Work on advanced verification methodologies like SV/UVM.
  6. Perform functional coverage driven verification closure.
  7. Working with architects, designers, and pre and post silicon verification teams to accomplish your tasks.

Skills

Required

  • B.Tech./ M.Tech., or equivalent experience
  • 5+ years of relevant experience
  • Experience in verification of complex IPs/units and sub-systems
  • Background in verification using random stimulus along with functional coverage and assertion-based verification methodologies
  • Expertise in Verilog
  • Knowledge in SystemVerilog or similar HVL / UVM or VMM

Nice to have

  • Experience in memory subsystem or network interconnect IP verification
  • Good debugging and analytical skills
  • Sound scripting knowledge
  • Good communication
  • Excellent team player