Senior Layout Design Engineer

at Intel · Industrial · Guadalajara, Mexico

Senior Layout Design Engineer at Intel in Guadalajara, Mexico, focusing on semiconductor physical design.

What you'd actually do

  1. Responsible for the physical design of integrated circuits, including layout, routing, and verification.
  2. Collaborate with circuit designers and verification engineers to ensure design meets specifications.
  3. Develop and maintain layout design flows and methodologies.
  4. Mentor junior engineers and provide technical guidance.
  5. Stay up-to-date with the latest advancements in semiconductor technology and design tools.

Skills

Required

  • Experience in IC layout design
  • Proficiency in Cadence Virtuoso or similar layout tools
  • Understanding of semiconductor fabrication processes
  • Knowledge of DRC/LVS and other physical verification rules
  • Strong problem-solving and analytical skills

Nice to have

  • Experience with scripting languages (e.g., Perl, Python)
  • Familiarity with advanced nodes (e.g., 7nm, 5nm)
  • Experience in analog or mixed-signal layout design

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