Senior Layout Design Engineer

Intel Intel · Semiconductors · Bangalore, India

Senior Layout Design Engineer at Intel responsible for designing complex analog signal circuit layouts, performing design verification, and developing new layout methodologies. Requires strong VLSI and custom/analog layout design experience.

What you'd actually do

  1. Designs complex layouts of analog signal circuits for a given design specification and runs complete set of design verification tools for process design rules, electron migration, voltage drop (IR), ESD, and other reliability checks on the layouts.
  2. Designs and analyzes floorplans, power grid, ESD, bumps, and performs all required verification on the analog blocks.
  3. Performs the microfloor planning and detail signal planning of complex analog circuits to meet performance and electrical requirements (shielding, matching) for critical signals to optimize for area, power, RV, and performance.
  4. Develops and drives new and innovative analog layout methodologies to improve layout productivity and quality.
  5. Collaborates with analog circuit design, process technology, and package design teams to meet design specifications, plan work, and negotiate layout tradeoffs as needed.

Skills

Required

  • VLSI design knowledge
  • circuit design knowledge
  • custom/analog layout design
  • layout validation including DRCs, density, antenna etc.
  • RV, high voltage flows and noise fixes
  • Charge pump, LDO, VDC, ADC or similar AMS layouts
  • Virtuoso XL

Nice to have

  • Scripting skills
  • fusion compiler based PNR