Senior Lead Ip Design Engineer

AMD AMD · Semiconductors · Bangalore, India · Engineering

This role is for a Senior Lead IP Design Engineer at AMD, focusing on micro-architecting, designing, and delivering data fabric IP RTL components. The engineer will manage power, performance, and area requirements, working with architecture, verification, and physical design teams to ensure silicon success. The role involves defining features, digital design implementation, RTL coding, leading design domains, and post-silicon support. Experience in fabric/transport architecture, coherency, and memory/cache design is preferred.

What you'd actually do

  1. Define Data Fabric features and capabilities required to meet SoC requirements on power, performance, Area targets
  2. Digital design implementation and micro-architecture of components of the Infinity Data Fabric, including cache design .
  3. Micro-architecture and RTL coding in Verilog/SystemVerilog .
  4. Lead design on one or more domains
  5. Work with architects and design leads to identify and assess complex technical issues

Skills

Required

  • Verilog/SystemVerilog
  • RTL Design
  • Digital design implementation
  • Micro-architecture
  • Power, Performance, Area (PPA) targets
  • SoC requirements
  • Verification
  • Physical Design
  • Post silicon support

Nice to have

  • fabric /transport architecture
  • coherency
  • memory design
  • cache design