Senior Logic Design Engineer

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA

Senior Logic Design Engineer role focused on FPGA/CPLD development, including micro-architectural definition, RTL coding, logic debug, synthesis, and timing closure. Responsibilities also include supporting verification, implementation, system bring-up, and validation. The role is within the DGX FPGA Logic Team, contributing to Data Center products for AI growth.

What you'd actually do

  1. Collaborating with the system architecture team to develop FPGA/CPLD design requirements and implement design to meet all specifications and targets.
  2. Writing readable high-quality RTL, synthesis, timing closure, design documentation, schematic review, bring-up, and supporting system-level validation/debug in the lab.
  3. Collaborating with our design verification and formal verification team to confirm the accuracy of your design.
  4. Working together with the validation team to carry out in-system tests and measurements in the lab.
  5. Assisting with overall FPGA design activities.

Skills

Required

  • Bachelor's Degree in Electrical Engineering, Computer Engineering, or Computer Science or equivalent experience
  • 5+ years of experience in FPGA/CPLD and/or ASIC semiconductor designs
  • Verilog/System Verilog expertise
  • deep understanding of ASIC/FPGA/CPLD development flow including RTL development, verification, logic synthesis, prototyping, DFT, timing analysis, and lab bring-up/debug
  • Strong communication and interpersonal skills
  • ability to work in a dynamic, distributed team
  • Direct involvement in system bring-ups

Nice to have

  • proven experience mentoring junior engineers and interns
  • A solid foundation in FPGA/CPLD development
  • familiarity with FPGA EDA tools from Xilinx, Altera, or Lattice like Vivado, Quartus, or Diamond
  • Familiarity with industry-standard protocols such as I2C, SPI, JTAG, PCIE, USB, Ethernet, Encryption
  • languages such as embedded C, Python, Perl
  • systems-thinking approach to hardware development
  • Platform and system design: Strong understanding or practical experiences with system design methodologies including board design, SI and familiarity with schematics and layout tools.
  • Cross-functional collaboration: Excel in cross-functional collaboration between firmware and hardware teams
  • Automation and AI: Ability to adopt AI to automate tasks efficiently, which includes but not limited to RTL generation, FPGA/CPLD build process and system level validation.

What the JD emphasized

  • Verilog/System Verilog expertise required
  • deep understanding of ASIC/FPGA/CPLD development flow including RTL development, verification, logic synthesis, prototyping, DFT, timing analysis, and lab bring-up/debug
  • Strong communication and interpersonal skills are required
  • proven experience mentoring junior engineers and interns is a significant advantage
  • Direct involvement in system bring-ups