Senior Logic Design Engineer, Cache Coherent Interconnects

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA +1

Senior Logic Design Engineer responsible for the design of CPU on-chip and off-chip interconnect network, MP coherency and last-level and system caches, focusing on micro-architectural definition, RTL coding, logic debug, synthesis and timing closure. Supports verification and implementation. Impacts product lines from consumer graphics to self-driving cars and AI.

What you'd actually do

  1. As a member of our core CPU team, you'll own and be responsible for crafting and timely delivery of a specific unit on the chip.
  2. Day to day tasks include: writing readable high performance and low power RTL, Synthesis and Timing closure, and design documentation.
  3. Collaborate with our verification team to verify the correctness of your unit.
  4. Work with implementation to achieve your timing, area, performance and power goals.
  5. Assist with timing closure of super units.

Skills

Required

  • Master’s Degree in Electrical Engineering, Computer Engineering or Computer Science or equivalent experience
  • 5+ years of experience in processor or other related high performance semiconductor designs
  • Verilog expertise
  • deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug
  • Strong communication and interpersonal skills

Nice to have

  • A strong background in computer architecture, cache coherency or high speed interconnects
  • mentoring junior engineers and interns

What the JD emphasized

  • Verilog expertise required
  • deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug
  • Strong communication and interpersonal skills are required