Senior Logic Design Verification Engineer

Intel Intel · Semiconductors · Penang, Malaysia

Senior Logic Design Verification Engineer responsible for developing verification testbenches, RTL models, and test content for power management controller IPs. The role involves validating new architectural features, debugging RTL tests, and collaborating with cross-organizational partners. Requires at least 8 years of experience with UVM and System Verilog.

What you'd actually do

  1. As a member of the PMC Logic Design Verification team, you will work closely with IP architects to define and develop verification testbench and building RTL models for verification.
  2. You will be validating and verifying the functionality of new architectural features of next generation designs by developing testplan, tests content or test tools.
  3. You will be finding and implementing corrective measures for failing RTL tests, analyzes and uses results to modify testing.
  4. Your influence will cross-organizational boundaries with our manufacturing and validation partners.
  5. Your expertise will grow as you debug and resolve issues on system platforms using software and RTL simulation tools.

Skills

Required

  • Bachelor's, Master's degree or Ph.D. in Electronics Engineering, Computer Engineering, or equivalent
  • 8 years of relevant working experience in IP/SoC design or verification development
  • UVM
  • System Verilog
  • UVM Verification Components
  • Bus-functional Models (BFM)
  • building Testbench from ground up
  • analysis skills
  • debugging skills
  • problem solving

Nice to have

  • UVM Virtual Sequencer
  • Factory
  • Formal Property
  • Assembly language
  • embedded firmware
  • real-time operating system RTOS
  • BIOS
  • HW/SW interactions
  • ACPI spec
  • power management
  • Hardware-Firmware co-validation
  • Linux
  • Python
  • Perl
  • simulation tools
  • Agile

What the JD emphasized

  • At least 8 years of relevant working experience in design verification with UVM and System Verilog.