Senior Logic Design Verification Engineer

Intel Intel · Semiconductors · Penang, Malaysia

Senior Logic Design Verification Engineer at Intel in Malaysia, focusing on Power Management Controller IP (PMC). Responsibilities include defining and developing verification testbenches, building RTL models, validating architectural features, and resolving RTL test failures. Requires extensive experience with UVM and System Verilog.

What you'd actually do

  1. You will work closely with IP architects to define and develop verification testbench and building RTL models for verification
  2. You will be validating and verifying the functionality of new architectural features of next generation designs by developing testplan, tests content or test tools
  3. You will be finding and implementing corrective measures for failing RTL tests, analyzes and uses results to modify testing
  4. Your influence will cross-organizational boundaries with our manufacturing and validation partners
  5. Your expertise will grow as you debug and resolve issues on system platforms using software and RTL simulation tools

Skills

Required

  • Bachelor's, Master's degree or Ph.D. in Electronics Engineering, Computer Engineering, or equivalent
  • 15 years of relevant working experience in design verification
  • UVM
  • System Verilog
  • IP/SoC design or verification development
  • UVM Verification Components
  • Bus-functional Models (BFM)
  • building Testbench from ground up
  • analysis skills
  • debugging skills
  • creative in problem solving
  • Motivated
  • Self-driven
  • Independent
  • Hardware-Firmware co-validation development and debugging environments
  • Linux
  • industry scripting languages (Python, Perl)
  • simulation tools
  • strong written and verbal communication skills
  • tolerance of ambiguity
  • problem solving
  • teamwork
  • attention to detail
  • commitment to task
  • quality focus
  • Knowledge of Agile

Nice to have

  • UVM Virtual Sequencer
  • Factory
  • Formal Property
  • Assembly language
  • embedded firmware
  • real-time operating system RTOS
  • BIOS
  • HW/SW interactions
  • ACPI spec
  • power management

What the JD emphasized

  • At least 15 years of relevant working experience in design verification with UVM and System Verilog