Senior Low Power Engineer – Physical Design & Pnr Flows

AMD AMD · Semiconductors · Hyderabad, India · Engineering

This role is for a Senior Low Power Engineer focused on Physical Design & Place and Route (PnR) flows at AMD. The engineer will be responsible for developing and automating low-power PnR flows for advanced technology nodes (3nm & 2nm), collaborating with design teams and EDA vendors, and supporting global design teams on P&R and ECO implementations. The role requires expertise in power grid construction, low-power implementation methodologies, and scripting for automation.

What you'd actually do

  1. Develop and maintain Power Grid (PG) construction and augmentation methodologies, including macro-PG tapping, PG EM/IR analysis and associated PG DRC closure
  2. Define and implement low‑power Place & Route flows supporting power gating and multi‑voltage domain designs
  3. Design and develop scripts and utilities to automate key components of the low‑power physical implementation flow
  4. Drive CAD low‑power flow and methodology development for advanced technology nodes, with preference for 3nm and 2nm process technologies
  5. Collaborate closely with synthesis, P&R, and signoff teams (STA, extraction, Physical Verification) to deliver best‑in‑class Power, Performance, and Area (PPA)
  6. Support global design teams on low‑power P&R and ECO implementations across multiple projects

Skills

Required

  • Master’s/Bachelor’s Degree in Electronics Engineering
  • 8-10 years of experience in CAD flow and methodology development on advanced nodes
  • Strong problem-solving skills
  • analytical thinking
  • Team player
  • good work ethic
  • excellent communication skills
  • Python
  • TCL
  • Perl
  • Synopsys Fusion Compiler
  • Cadence Innovus

Nice to have

  • Minor in Computer Science
  • Extensive hands‑on experience with power gating and multi‑voltage design architectures
  • Strong understanding of low‑power implementation methodologies, including UPF, power gating, isolation strategies, level shifters, voltage areas, and power‑state tables
  • strong debugging capabilities
  • CAD‑automation mindset
  • Exposure to AI/ML concepts

What the JD emphasized

  • low-power Place & Route flows
  • 3nm and 2nm process technologies