Senior Lpu Asic Engineer

NVIDIA NVIDIA · Semiconductors · CA +5 · Remote

Senior LPU ASIC Engineer role at NVIDIA, focusing on full-flow physical design of large-scale, high-performance SoCs at advanced process nodes. Responsibilities include synthesis, floorplanning, place & route, timing constraints, UPF, LEC, PPA optimizations, and tapeout execution. Requires expertise in low-power design, clock & timing, sign-off, and scripting for automation. Experience with AI-driven optimizations for design efficiency is a plus.

What you'd actually do

  1. Full-Flow Ownership: Responsible for Synthesis, floorplanning, place & route, timing constraints, UPF and LEC at the block/partition level and top level.
  2. Cross-Functional Optimization: Partner with IP, Front-End logic design and Architecture teams to streamline IP integration, drive PPA (Power, Performance, Area) optimizations, resolving architectural bottlenecks to enable efficient physical implementation.
  3. Tapeout Execution: Lead design closure in collaboration with IP, PnR, Sign-off teams, ensuring 100% verification compliance for successful GDSII handoff and tapeout.
  4. Methodology Innovation: Architect data-driven EDA flows and methodologies in collaboration with CAD teams, implementing automated enhancements that measurably improve PPA and design cycle efficiency.

Skills

Required

  • B.S. in Electrical/Computer Engineering or equivalent experience
  • 5+ years of industry experience
  • Full-Flow Execution (synthesis, placement, CTS, routing, extraction, physical/electrical verification)
  • Low-power design intent (UPF/CPF)
  • Formal equivalency checks (LEC)
  • Clock tree synthesis
  • Sign-off timing analysis (MCMM STA)
  • Advanced CTS methodologies
  • Complex constraints
  • Aggressive power, performance and area optimization techniques
  • Power grid design
  • EMIR analysis
  • ECO generation
  • DFT structures
  • Scripting (TCL, Python, Perl)
  • Industry-standard tool suites for end-to-end physical design flows

Nice to have

  • M.S./Ph.D.
  • AI-driven optimizations for enhanced design efficiency
  • High-speed SerDes IPs (PCIe, CXL, C2C, Die-to-Die interfaces)

What the JD emphasized

  • delivering full-flow physical design for large-scale, high-performance SoCs at advanced process nodes
  • Full-Flow Execution
  • Low-Power Expertise
  • Clock & Timing Mastery
  • PPA Optimization
  • Sign-off & Integrity
  • DFT & Block-Level Integration
  • EDA Tool Proficiency
  • Automation & Innovation
  • High-Speed IP Integration