Senior Manager, System Integration – Silicon Co-design Group

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA

Senior Manager for System Integration in NVIDIA's Silicon Co-Design Group, focusing on post-silicon bring-up, debug, and validation across various NVIDIA product lines (GPU, SoC, CPU). The role involves leading teams to find critical silicon issues earlier, manage program timelines despite dependencies, and build operational rigor. Experience in leading technical teams, system-level post-silicon debug, and cross-functional collaboration is required.

What you'd actually do

  1. Plan and execute post-silicon feature integration, PVT validation, and wide-area testing across NVIDIA’s GPU, SoC, and CPU programs.
  2. Build wide-area and in-system test as a repeatable capability that shifts post-silicon coverage left, so issues surface before we are production-ready.
  3. Lead resolution of the most complex system-level issues, RMAs, and HW/SW interaction problems with creative workarounds and focused lab experimentation.
  4. Develop new strategies to keep programs on milestone when upstream dependencies — software, firmware, methodology, validation — slip.
  5. Hire, mentor, and retain senior technical talent. Build a strong bench and grow individual contributors into the next generation of senior technical leaders.

Skills

Required

  • Bachelor's or Master’s in Electrical or Computer Engineering (or equivalent experience)
  • 12+ years of system-level post-silicon bring-up and debug experience
  • 5 years leading technical teams
  • shipped silicon experience
  • Direct experience finding critical silicon issues before software was production-ready
  • building or scaling wide-area or in-system test programs
  • Led technical teams across multiple geographies
  • attracting, growing, and retaining senior technical talent
  • Strong EE fundamentals (DFT, digital design, computer architecture, power, timing, fault analysis)
  • translate complex technical issues into clear options for executive audiences

Nice to have

  • process and methodology improvements
  • partnering deeply with a counterpart team in India or another major engineering hub
  • DFT experience with system-test features for in-field test on production silicon
  • familiarity with fault models, DPPM, quality metrics, and RAS
  • redesigning how a team works with AI

What the JD emphasized

  • critical silicon issues earlier
  • Left-shifting post-silicon coverage
  • repeatable capability
  • keep programs on milestone
  • upstream dependencies slip
  • shipped silicon