Senior Mask Design Engineer

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA

Senior Mask Layout Design Engineer to perform physical layout for mixed-signal functions in sub-micron CMOS technologies using Cadence tools. Responsibilities include floor planning, custom layout, verification against design rules and schematics, fill, post-processing, DRC mitigation, and foundry interactions.

What you'd actually do

  1. Perform physical layout for mixed-signal functions like PLL's, high speed I/O circuits, general I/O's, ESD structures designs in innovative sub-micron CMOS technologies using Cadence tools
  2. You'll work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.
  3. Job duties will include floor planning, custom layout and verifying against design rules and schematics.
  4. Fill, post-processing, DRC mitigation, and foundry interactions

Skills

Required

  • BS in Electrical Engineering (or equivalent experience)
  • 6+ years of hands-on layout design experience
  • Analog circuit layout concepts in submicron CMOS technologies
  • Cadence custom circuit design tools - virtuoso
  • DRC and LVS verification tools (Dracula, Hercules, Calibre, Primeyield)
  • Scripting languages (perl, python, skill)
  • DRC and LVS checking flows

Nice to have

  • Ability to work optimally in a team
  • Good interpersonal skills
  • Positive energy

What the JD emphasized

  • At least 6+ years of hands-on layout design experience
  • Deep understanding of analog circuit layout concepts in submicron CMOS technologies
  • Experience running and debugging DRC and LVS with verification tools such as Dracula, Hercules, Calibre, Primeyield
  • Proficiency in scripting languages like perl, python, skill etc.
  • Knowledge of DRC and LVS checking flows, ability to customize DRC and LVS