Senior Mask Design Engineer - Hardware

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA

Senior Mask Layout Design Engineer responsible for physical layout of mixed-signal functions in advanced CMOS technologies using Cadence tools, collaborating with ASIC and mixed-signal engineers, and performing floor planning and verification.

What you'd actually do

  1. Performing physical layout for mixed-signal functions like PLL's, high speed SerDes, Analog to Digital converters, ESD structures designs in innovative sub-micron CMOS technologies using Cadence tools.
  2. You'll work multi-functional with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.
  3. Take part in floor planning, custom layout and verifying against design rules and schematics.

Skills

Required

  • BSEE or equivalent experience
  • 8+ years industry experience
  • Analog circuit layout concepts in submicron CMOS technologies
  • Cadence custom circuit design tools
  • Verification tools (Dracula, Hercules, Calibre, Primeyield)
  • Scripting languages (perl, python, skill)
  • DRC and LVS checking flows

Nice to have

  • good interpersonal skills
  • passion and positive energy

What the JD emphasized

  • minimum of 8+ years industry experience
  • Deep understanding of analog circuit layout concepts in submicron CMOS technologies
  • You are an authority with Cadence custom circuit design tools
  • Experience running and debugging with verification tools such as Dracula, Hercules, Calibre, and Primeyield
  • Proficient in scripting languages like perl, python, skill etc.
  • Should have knowledge of DRC and LVS checking flows, ability to customize decks