Senior Mask Design Engineer - Hardware

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA

Senior Mask Layout Design Engineer for chiplet interface projects, focusing on physical layout of mixed-signal functions using Cadence tools in advanced CMOS technologies.

What you'd actually do

  1. Performing physical layout for mixed-signal functions like top level, high speed datapaths and high-speed clocking designs in state-of-the-art sub-micron CMOS technologies using Cadence tools.
  2. You'll work closely with mixed-signal design engineers to customize designs for integration in VLSI products.
  3. Take part in floor planning, custom layout and verifying against design rules and schematics.

Skills

Required

  • BSEE or equivalent experience
  • 8+ years industry experience in Mask and Layout Design
  • FinFET technology
  • Cadence custom circuit design tools (virtuoso)
  • DRC and LVS checking flows
  • Ability to customize decks

Nice to have

  • perl
  • python
  • skill

What the JD emphasized

  • Deep understanding and previous experience for FinFET technology is a must
  • You are an authority with Cadence custom circuit design tools - particularly virtuoso.