Senior Mask Layout Design Engineer

NVIDIA NVIDIA · Semiconductors · Hsinchu, Taiwan +1

Senior Mask Layout Design Engineer to perform physical layout for mixed-signal functions in state-of-the-art sub-micron CMOS technologies using Cadence tools. Responsibilities include working with design engineers, floor planning, custom layout, and verifying against design rules and schematics.

What you'd actually do

  1. Performing physical layout for mixed-signal functions like top level, high speed datapaths and high-speed clocking designs in state-of-the-art sub-micron CMOS technologies using Cadence tools.
  2. You'll work closely with mixed-signal design engineers to customize designs for integration in VLSI products.
  3. Take part in floor planning, custom layout and verifying against design rules and schematics.

Skills

Required

  • BSEE or equivalent experience
  • Minimum of 5+ years industry experience in Mask and Layout Design
  • Working independently on creating layout with excellent quality
  • Deep understanding and previous experience for FinFET technology
  • Cadence custom circuit design tools - particularly virtuoso
  • Able to handle fast-paced project and iterate quickly based on designer’s feedback
  • You can work effectively in a team, good interpersonal skills, enthusiasm, and positive energy.
  • knowledge of DRC and LVS checking flows, ability to customize decks

Nice to have

  • Scripting languages like perl, python, skill etc.

What the JD emphasized

  • Deep understanding and previous experience for FinFET technology is a must