Senior Mask Layout Design Engineer

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA +1 · Remote

NVIDIA is seeking a Senior Mask Layout Design Engineer to perform physical layout for digital and mixed-signal functions in sub-micron CMOS technologies using Cadence tools. The role involves collaborating with circuit designers, performing floor planning, custom layout, verification, and mitigating DRC issues. Leadership experience in mentoring junior designers and implementing standard processes is also required.

What you'd actually do

  1. Perform physical layout for digital and mixed-signal functions like clock generators, op-amps, sensors, security circuits, power delivery circuits in state-of-the-art sub-micron CMOS technologies using Cadence tools
  2. You'll work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.
  3. Job duties will include floor planning, custom layout and verifying against design rules and schematics.
  4. Fill, post-processing, DRC mitigation, and foundry interactions

Skills

Required

  • BS in Electrical Engineering
  • 7+ years of hands-on layout design experience
  • Deep understanding of analog circuit layout concepts in submicron CMOS technologies
  • Validated experience with Cadence custom circuit design tools - particularly virtuoso
  • Experience running and debugging DRC and LVS with verification tools such as Dracula, Hercules, Calibre
  • Communicate with diverse team of mask designers across geographies and timezones.
  • Ability to work optimally in a team, good interpersonal skills and positive energy.

Nice to have

  • Proficiency in scripting languages like perl, python, skill etc.
  • Knowledge of layout automation

What the JD emphasized

  • Leadership experience mentoring and assisting junior mask designers, implementing standard processes for the team, and keeping checklists for optimal layout design.