Senior Mask Layout Design Engineer

NVIDIA NVIDIA · Semiconductors · Hsinchu, Taiwan +1

Senior Mask Layout Design Engineer to perform physical layout for mixed-signal functions like PLL's, high speed I/O circuits, general I/O's, ESD structures designs in state-of-the-art sub-micron CMOS technologies using Cadence tools. Work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products. Job duties will include floor planning, custom layout and verifying against design rules and schematics.

What you'd actually do

  1. Perform physical layout for mixed-signal functions like PLL's, high speed I/O circuits, general I/O's, ESD structures designs in state-of-the-art sub-micron CMOS technologies using Cadence tools.
  2. You will work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.
  3. Job duties will include floor planning, custom layout and verifying against design rules and schematics.

Skills

Required

  • BSEE or equivalent experience
  • 5+ years of relevant mask design / layout experience
  • Deep understanding of analog circuit layout concepts in submicron CMOS technologies
  • Cadence custom circuit design tools - virtuoso
  • DRC and LVS verification tools (Dracula, Hercules, Calibre, Primeyield)
  • Scripting languages (perl, python, skill)
  • DRC and LVS checking flows
  • Ability to customize DRC and LVS decks

Nice to have

  • Good communication skills
  • Enthusiasm and positive energy

What the JD emphasized

  • Minimum of 5+ years of relevant mask design / layout experience
  • Deep understanding of analog circuit layout concepts in submicron CMOS technologies
  • expert with Cadence custom circuit design tools - particularly virtuoso
  • Experience running and debugging DRC and LVS with verification tools such as Dracula, Hercules, Calibre, Primeyield
  • Knowledge of DRC and LVS checking flows, ability to customize DRC and LVS decks