Senior Memory Controller Verification Engineer

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA +4

Senior Verification Engineer for NVIDIA's GPU Memory Subsystem IP verification Team. Responsibilities include developing verification infrastructure, executing test plans for features and performance, ensuring coverage, and supporting post-silicon verification. Requires 5+ years of ASIC verification experience with System Verilog and UVM.

What you'd actually do

  1. Develop verification infrastructure (testbenches, BFMs, checkers, monitors, randoms)
  2. Come up with, review and drive test plan execution for planned features
  3. Understand the performance requirements of your IP, come up with, review and drive performance testplan for your IP
  4. Ensure code and functional coverage of all the RTL which you will verify.
  5. Work with and enable FPGA and software teams to ensure that software is tested.

Skills

Required

  • BS / MS or equivalent experience
  • 5+ years of ASIC verification experience
  • Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB)
  • System Verilog
  • UVM based methodology for ASIC verification

Nice to have

  • Strong C/C++ programming experience
  • Prior Design or Verification experience of dynamic memory controllers (ddr{2, 3, 4, 5}, lpddr{2, 3,4,5,6}, HBM, or GDDR)
  • Strong debugging and problem solving skills
  • Scripting knowledge (Python/Perl/shell)
  • Good interpersonal skills and ability & desire to work as a part of a team

What the JD emphasized

  • 5+ years of ASIC verification experience of complex design units displaying good attention to detail, teamwork, problem solving and shown success