Senior Mixed Signal Circuit Design Engineer

NVIDIA NVIDIA · Semiconductors · Hsinchu, Taiwan +1

NVIDIA is seeking a Senior Mixed Signal Design Engineer to join their Mixed Signal design team building next generation NVLINK. This role involves the design, simulation, verification, and characterization of high-speed interface circuits and analog circuits, with a focus on transceivers and PLLs for data rates of 100Gbps and higher. The engineer will lead mask designers, mentor junior engineers, and take designs from concept through silicon characterization and productization. Experience with deep submicron CMOS processes, Cadence tools, and silicon bring-up is required.

What you'd actually do

  1. You will be part of the design and implementation of high-speed interface circuits; Have the chance to create projects including high speed transceivers and high frequency PLLs.
  2. Become involved in the design, simulation, and verification of mixed-signal circuits; Lead mask designers, provide mentorship for floorplan and layout design.
  3. Provide support to the lab characterization of silicon and pursue the challenges of circuit design in deep submicron CMOS.
  4. You will take designs through implementation and productizing.
  5. Collaborate with multi-functional teams.

Skills

Required

  • BS or MS in Electrical Engineering, PhD preferred (or equivalent experience)
  • 5+ years of design experience in CMOS analog / mixed-signal circuit
  • Working knowledge of Cadence custom design tools, circuit simulator, timing analysis tool
  • extensive design experience in Data Converters, Tx, Rx, CDR, PLL for high-speed IO interfaces
  • exceptional teammate with good interpersonal skills
  • Validated experience in leading and mentoring designers
  • In-depth understanding of deep submicron CMOS process and related circuit design issues
  • Proven experience in silicon bring-up, debugging and use of lab instrumentation is required

Nice to have

  • Knowledge in system level timing budget, signal integrity, and power integrity is a plus
  • Experience in Verilog, Matlab, Nanotime is helpful

What the JD emphasized

  • 5+ years of design experience in CMOS analog / mixed-signal circuit
  • extensive design experience in Data Converters, Tx, Rx, CDR, PLL for high-speed IO interfaces
  • Proven experience in silicon bring-up, debugging and use of lab instrumentation is required