Senior Mixed Signal Circuit Design Engineer

NVIDIA NVIDIA · Semiconductors · Hsinchu, Taiwan +1

NVIDIA is seeking a Senior Mixed Signal Circuit Design Engineer to architect, build, and implement high-speed Serdes reaching 80Gbps and beyond. The role involves full ownership of the silicon lifecycle, from concept to characterization, with a focus on optimizing complex circuits in deep-submicron CMOS and FinFET technologies. Collaboration with layout engineers and post-silicon debugging are key responsibilities.

What you'd actually do

  1. Architect the Future: Take full ownership of high-speed Serdes architectures and transistor-level builds, pushing data rates to 80Gbps and higher.
  2. Silicon Ownership: Drive the entire lifecycle—from initial concept and schematic entry to layout, verification, and final silicon characterization.
  3. Master the Physics: Optimize complex circuits for peak system performance, balancing noise, power, and loop stability in deep-submicron nodes.
  4. Collaborative Precision: Partner closely with layout engineers to provide strategic floorplanning and high-speed routing mentorship that ensures design integrity.
  5. Solve the Impossible: Lead post-silicon bring-up and debugging efforts, translating real-world data into build refinements.

Skills

Required

  • MS in Electrical Engineering, Computer Engineering, or related field, or equivalent practical experience
  • Minimum 5 plus years of professional Analog Build experience
  • deep portfolio in FinFET and deep-submicron CMOS processes
  • Proficiency in the Cadence Virtuoso environment
  • black belt in simulation tools (Spectre, HSpice, FineSim, or XA)
  • Expertise in noise analysis, Monte Carlo simulations, and complex loop stability
  • Rich experience in high-speed data and/or clock path design
  • Proven ability in the modeling, timing, and functionality of both analog and digital circuits
  • collaborative teammate who communicates clearly and solves problems with a "find a way" mentality

What the JD emphasized

  • high-speed Serdes
  • 80Gbps
  • deep-submicron CMOS
  • FinFET technology
  • transistor-level builds
  • silicon characterization
  • post-silicon bring-up and debugging