Senior Mixed Signal Design Engineer

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA

Senior Mixed-Signal/Analog/IO Circuit Design Engineer at NVIDIA, focusing on high-speed memory interface designs within deep submicron CMOS FinFET processes. Requires 8+ years of experience in memory or SerDes related design, system-level timing analysis, and Cadence tools. Familiarity with package substrate, board design, and power delivery is a plus.

What you'd actually do

  1. Mixed-Signal/Analog circuit build for High Speed Memory I/O Interfaces
  2. Solve challenge of circuit development in deep submicron CMOS FinFET processes
  3. Take designs through productization and be involved in all stages of development
  4. Work with multi-functional teams to optimize the designs

Skills

Required

  • BSEE or MSEE or equivalent experience
  • 8+ years of well-rounded high Speed memory (LPDDR, DDR, GDDR, HBM) or SerDes related design experience
  • System level timing budgets, specs and analysis
  • In-depth understanding of deep submicron CMOS FinFET process and circuit design issues
  • Familiarity with device reliability, ESD and Latch-Up requirements
  • Lead layout development and understand all ESD/Latch-Up, reliability rules
  • Broad circuit design and implementation knowledge with significant depth
  • Strong background of Cadence custom design tools, various circuit simulators like Hspice, XA, FineSim, Spectre

Nice to have

  • Working Knowledge of package substrate, board design and power delivery is a plus
  • Solid understanding of Verilog, Nanotime, Matlab is plus
  • Hands on with Lab test and measurement equipment is a plus

What the JD emphasized

  • high Speed memory (LPDDR, DDR, GDDR, HBM) or SerDes related design experience