Senior Mixed Signal Design Engineer

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA

NVIDIA is hiring a Senior Mixed-signal Design Engineer to work on high-speed I/O SerDes technology for GPUs that enable AI, deep learning, and autonomous driving. The role involves creating systemVerilog models of analog components, defining system architecture, and scripting for efficiency. Requires 5+ years of experience in high-speed I/O digital design, understanding of Verilog/SystemVerilog, mixed-signal blocks, Serdes/PLL analog design, and scripting languages like Perl and Python. FPGA emulation experience is a plus.

What you'd actually do

  1. Work with analog designers to create accurate systemVerilog model of analog components such as closed-loop PLL, Rx CTLE, SAR ADC and also optics components.
  2. You’ll work with system architects, digital designers to define and verify the system architecture specification and refine adaptation algorithms.
  3. Help in streamlining workflows with proper scripts to increase efficiency and enables reusability
  4. Be actively involve in silicon bringup, build scripts that can be used for debug, QA, characterization and ATE

Skills

Required

  • B.S. or MS degree in Electrical Engineering or equivalent experience
  • 5+ years of experience working in high-speed I/O digital design
  • knowledge at protocol level (SATA, PCIE, USB) preferred
  • Deep understanding of Verilog or SystemVerilog, logic design and circuit modeling for mixed-signal blocks
  • Deep understanding of high-speed Serdes/PLL analog circuit design.
  • Proven experience with custom digital circuit design and adaptation algorithms, such as DFE, CTLE, CDR, and offset cancellation
  • Strong background in Perl and Python scripting

Nice to have

  • FPGA emulation experience is a plus

What the JD emphasized

  • 5+ years of experience working in high-speed I/O digital design
  • Deep understanding of Verilog or SystemVerilog, logic design and circuit modeling for mixed-signal blocks
  • Deep understanding of high-speed Serdes/PLL analog circuit design.
  • Proven experience with custom digital circuit design and adaptation algorithms, such as DFE, CTLE, CDR, and offset cancellation
  • Have a strong background in Perl and Python scripting