Senior Mixed Signal Design Engineer

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA

NVIDIA is seeking a Senior Mixed-Signal/Analog/IO Circuit Design Engineer to work on High-Speed Memory I/O Interfaces using the latest CMOS FinFET processes. The role involves designing, productizing, and optimizing circuits, contributing to architecture definition, and collaborating with multi-functional teams. Requires 4+ years of experience in high-speed DRAM or SerDes interfaces, with a strong understanding of CMOS FinFET processes and circuit design issues. Familiarity with system-level timing, package substrate, board development, and power delivery is a plus. Experience with Cadence tools, simulators, Verilog, Matlab, and silicon debug is also beneficial.

What you'd actually do

  1. Mixed-Signal/Analog circuit design for High-Speed Memory I/O Interfaces
  2. Solve challenges of circuit designs in the latest CMOS FinFET processes
  3. Take designs through productization and be actively involved in all stages of development
  4. Work with multi-functional teams to optimize the design
  5. Contribute to the architecture definition and development of next-generation and future memory systems and interfaces

Skills

Required

  • MS/PhD in Electrical Engineering or equivalent experience
  • 4+ years of well-rounded high-Speed DRAM (LPDDR5/6, DDR4/5, GDDR5/6/7, HBM3/4) or other SerDes interface related design experience
  • In-depth understanding of deep submicron CMOS FinFET process and related circuit design issues
  • Familiarity with device reliability, ESD, and Latch-Up requirements
  • Possess an understanding of system-level timing budgets, specs, and analysis
  • Strong background of Cadence custom develop tools, various circuit simulators like Hspice, XA, FineSim, Spectre

Nice to have

  • Solid Understanding of the package substrate, board develop, and power delivery is a plus
  • Knowledge of Verilog, Nanotime, Matlab, or similar tools is a plus
  • Hands-on experience of silicon debug with Lab test and measurement equipment is a plus

What the JD emphasized

  • high-speed DRAM (LPDDR5/6, DDR4/5, GDDR5/6/7, HBM3/4) or other SerDes interface related design experience