Senior Mixed Signal Design Engineer

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA

NVIDIA is seeking a Senior Mixed Signal Design Engineer to architect, build, and implement high-speed Serdes reaching 80Gbps and beyond. The role involves full ownership from concept to silicon characterization, optimization of complex circuits, and leading post-silicon bring-up and debugging. Requires MS in EE or related field, 5+ years of Analog Build experience, proficiency in Cadence Virtuoso and simulation tools, and expertise in noise analysis, Monte Carlo simulations, and high-speed data/clock path design.

What you'd actually do

  1. Architect the Future: Take full ownership of high-speed Serdes architectures and transistor-level builds, pushing data rates to 80Gbps and higher.
  2. Silicon Ownership: Drive the entire lifecycle—from initial concept and schematic entry to layout, verification, and final silicon characterization.
  3. Master the Physics: Optimize complex circuits for peak system performance, balancing noise, power, and loop stability in deep-submicron nodes.
  4. Collaborative Precision: Partner closely with layout engineers to provide strategic floorplanning and high-speed routing mentorship that ensures design integrity.
  5. Solve the Impossible: Lead post-silicon bring-up and debugging efforts, translating real-world data into build refinements.

Skills

Required

  • MS in Electrical Engineering, Computer Engineering, or related field, or equivalent practical experience
  • Minimum 5 plus years of professional Analog Build experience
  • deep portfolio in FinFET and deep-submicron CMOS processes
  • Proficiency in the Cadence Virtuoso environment
  • black belt in simulation tools (Spectre, HSpice, FineSim, or XA)
  • Expertise in noise analysis, Monte Carlo simulations, and complex loop stability
  • Rich experience in high-speed data and/or clock path design
  • Proven ability in the modeling, timing, and functionality of both analog and digital circuits
  • collaborative teammate
  • communicates clearly
  • solves problems with a "find a way" mentality

What the JD emphasized

  • high-speed Serdes
  • 80Gbps and higher
  • deep-submicron CMOS
  • FinFET technology
  • Cadence Virtuoso
  • Spectre, HSpice, FineSim, or XA
  • noise analysis
  • Monte Carlo simulations
  • complex loop stability
  • high-speed data and/or clock path design