Senior Out-of-order Cpu Architect

Intel Intel · Semiconductors · Texas, Austin, United States

Senior Out-of-Order CPU Architect at Intel, responsible for defining and driving end-to-end CPU architecture specifications, exploring novel architectures, and influencing cross-functional roadmaps. Requires extensive experience in high-performance CPU design and out-of-order pipeline architecture.

What you'd actually do

  1. Develop and drive end-to-end CPU architecture specifications based on hardware features, requirements, and lifecycle needs.
  2. Define CPU targets for performance, power, frequency, area, and feature content to align with market requirements.
  3. Explore new approaches and devise novel architectures that deliver optimized CPUs for multiple segments, from high-performance computing to extreme low-power applications.
  4. Invent, conceptualize, and specify architectural and microarchitecture features that address future CPU usage and segment needs.
  5. Define and document new instructions to support innovative use cases and improve existing ones, enhancing the instruction set architecture (ISA).

Skills

Required

  • CPU architecture fundamentals
  • microarchitecture design
  • low-power design
  • RTL development
  • System Verilog
  • debug microarchitecture and simulation issues
  • solve complex design problems

Nice to have

  • Strong analytical and problem-solving skills
  • leadership roles or team management
  • Effective collaboration skills
  • influence cross-functional roadmaps
  • Passion for driving innovation

What the JD emphasized

  • 15+ consecutive years of experience within high performance/high frequency ARM or x86 CPU organizations working in either the design or architectural domain. Ideally both.
  • 10+ years of experience working within the out-of-order sections of the CPU pipeline. This includes the areas of wide instruction rename and allocation, uop/instruction schedulers, and execution units.
  • 5+ years writing RTL and owning it through timing and power convergence across multiple generations of a CPU line.
  • 2+ years of experience building deep, high frequency advanced integer and/or floating-point/vector schedulers.