Senior Package Layout Engineer

NVIDIA NVIDIA · Semiconductors · Hsinchu, Taiwan

NVIDIA is seeking a Senior Package Layout Engineer to design state-of-the-art high-speed interconnect systems for Supercomputers and Datacenters. The role involves collaborating on high-speed and PDN design for ASIC packages, developing symbols, pad stacks, and performing substrate package routing, placement, and power distribution using APD or SiP tools. Responsibilities include optimizing package pin-out, developing methodologies to improve layout productivity and reliability, and leading projects from start to finish. Requires a B.Sc. in Electrical Engineering or equivalent, 5+ years of experience in Package or PCB Layout with high-speed design, signal integrity, and PDN planning, and experience with substrate layout for wire bond and flip chip packages.

What you'd actually do

  1. As part of a Package Layout team, you will collaborate to implement high speed and PDN design for ASIC packages.
  2. Develop symbols, pad stack and perform substrate package routing, placement, stack-up, reference plane, power distribution using APD or SiP tools.
  3. Optimize package pin out incorporating system level trade-offs of pins assignment.
  4. Develop methodologies to improve layout environment, productivity, reliability, and schedule considerations.
  5. Planning, ensuring stakeholder management and leading projects from start to finish

Skills

Required

  • B.Sc. Electrical Engineering or any equivalent experience
  • Minimum of 5+ years hand-on in Package or/and PCB Layout
  • high speed design signal integrity practice
  • PDN designing and planning
  • Experience in substrate layout of wire bond and flip chip packages
  • Knowledge in substrates or board manufacturing process
  • Significant background with APD or SiP and/or other PCB layout tools
  • English communication skills (written and verbal)

Nice to have

  • Knowledge in Ansys (SIwave, HFSS) or Cadence (Sigrity, PowerSI) simulation tools
  • Familiarity with Skill language (Cadence) and basic parsing abilities (Python/Perl/Shell-scripting)

What the JD emphasized

  • Minimum of 5+ years hand-on in Package or/and PCB Layout
  • high speed design signal integrity practice
  • PDN designing and planning
  • Significant background with APD or SiP and/or other PCB layout tools