Senior Performance Verification Engineer

NVIDIA NVIDIA · Semiconductors · Bangalore, India

NVIDIA is seeking a Senior Performance Verification Engineer for their Networking Silicon Engineering team, focusing on SmartNICs and DPUs. The role involves full-chip verification of complex SoCs/NICs, with a strong emphasis on end-to-end performance metrics like throughput and latency. Responsibilities include identifying and mitigating performance bottlenecks, and architecting reusable testbench infrastructure. Requires 5+ years of experience in design verification, exposure to verification tools, and scripting knowledge. Experience in SoC/Subsystem Performance Verification, Specman, smartNICs, or high-speed interconnects is desirable.

What you'd actually do

  1. Perform full‑chip verification of complex SoC/NIC top‑level entities against micro‑architectural and interface specifications, with a strong focus on end‑to‑end performance metrics such as throughput and latency.
  2. Partner closely with design, architecture, and modeling teams to identify, analyze, and mitigate performance bottlenecks across the design pipeline.
  3. Architect and implement reusable testbench infrastructure components and develop targeted test scenarios for full‑chip NIC performance verification, leveraging deep understanding of NIC micro‑architecture and traffic flows.
  4. Use sophisticated verification methodologies like e-specman, SV-UVM etc.

Skills

Required

  • BS (or equivalent experience) / MS with 5+ years of experience in design verification
  • Exposure to design and verification tools (Verilog/SV or equivalent, Cadence or equivalent simulation tools, debug tools like Indago, GDB etc.)
  • Strong debugging, problem-solving and analytical skills
  • Scripting knowledge (Python/Perl/shell)

Nice to have

  • C/C++/UVM programming language experience desirable
  • Validated experience in SoC/Subsystem Performance Verification
  • Background in Specman
  • Any Prior experience of smartNIC and/or high-speed interconnects
  • Knowledge in HDL (Verilog/VHDL)