Senior Physical Design Backend Engineer

NVIDIA NVIDIA · Semiconductors · Yokneam, Israel +1

Senior Physical Design Backend Engineer at NVIDIA, focusing on high-speed communication chips. Responsibilities include chiplet STA, timing constraint generation, and resolving complex timing/congestion issues. Requires 5+ years of STA experience and familiarity with Prime Time.

What you'd actually do

  1. Own the special chiplet STA, analyze the timing results, verify correctness and provide budget for the different partitions.
  2. Generate the timing constraints for the STA and the P&R flow.
  3. Be exposed and work on a variety of exciting designs (including high cell count and high frequency), resolving complex timing and congestion problems.
  4. Help to shape clock tree, and effect the work of the different teams (Front end, DFT & BE).
  5. Daily work involves all aspect of STA & chip design: take part in SDC generation & review, actively running & analyzing STA tools, guiding the group during chip closure process, etc'.

Skills

Required

  • Physical Design
  • STA
  • Prime Time
  • Signoff methodologies
  • Physical construction and Integration

Nice to have

  • Clock tree shaping
  • SDC generation & review
  • Chip closure

What the JD emphasized

  • 5+ years of hands-on STA experience