Senior Physical Design Engineer

Microsoft Microsoft · Big Tech · Gelugor, Penang, Malaysia · Silicon Engineering

Senior Physical Design Engineer for Microsoft's Cloud Hardware and Infrastructure Engineering team, focusing on the design, development, manufacturing, and packaging of state-of-the-art computer chips for Azure. The role involves owning and driving floorplanning, synthesis, place and route, and signoff for Mixed-Signal IPs, with a focus on optimizing power, area, and timing.

What you'd actually do

  1. Own and drive floorplanning and design planning for optimizing Mixed-Signal IPs with Analog and Digital components
  2. Own and drive execution from synthesis to place and route of IPs, all signoff including timing signoff, physical verification, EMIR signoff , Formal Equivalence, and Low Power Verification.
  3. Define Analog / Digital interfaces to facilitate design convergence and optimize power delivery for optimal performance (topmetal & bump planning)
  4. Have close collaboration with RTL team to help drive and resolve design issues related to toplevel and block closure.
  5. Influence tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach.

Skills

Required

  • BS/MS in Electrical or Computer Engineering
  • 8+ years of experience
  • Experience in EDA tools such as Primetime, StarRC, Design Compiler, ICC, Innovus etc.
  • Strong understanding of constraints generation, STA, timing optimization, and timing closure.
  • Great communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.
  • Proven track record of implementing designs through synthesis, floorplanning, place and route, extraction, timing, and physical verification.

Nice to have

  • Experience in power rollup methodology and hand-on power rollup activities at block and fullchip level.
  • Tape-out experience in the latest foundry process nodes.
  • Excellent project management skills and ability to juggle multiple projects at once.
  • In-depth understanding of design tradeoffs for power, performance, and area.
  • Solid hands on experience with CTS and global clock distribution methods in multi-voltage, multi-clock, multi-domain, and low power designs.
  • Experience and knowledge of formal equivalency checks, LP, UPF, reliability, SI, and noise.
  • Strong problem-solving and data analysis skills
  • Strong automation skills using scripting languages such as Perl, TCL, Python.

What the JD emphasized

  • Silicon Manufacturing and Package Engineering