Senior Physical Design Engineer

NVIDIA NVIDIA · Semiconductors · Bangalore, India +1

NVIDIA is seeking a Senior Physical Design Engineer to lead block/chip level Physical Design (PD) activities for GPUs and ASICs. Responsibilities include floor plans, RC extraction, PNR, STA, EM, IR DROP, DRCs, and schematic to layout verification. The role requires 4+ years of experience in Physical Design, strong understanding of RTL2GDSII flow, expertise in high-frequency design, and proficiency in tools like ICC2/Innovus and Primetime/Tempus. Automation skills in PERL, TCL, or tool-specific scripting are also required.

What you'd actually do

  1. In this position, you will expected to lead all block/chip level PD activities.
  2. PD activities includes floor plans, abstract view generation, RC extraction, PNR, STA, EM,IR DROP, DRCs & schematic to layout verification. Work in collaboration with design team for addressing design challenges.
  3. Help team members in debugging tool/design related issues.
  4. Constantly look for improvement in RTL2GDS flow to improve PPA. Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention.
  5. Responsible for all aspects of physical design and implementation of GPU and other ASICs targeted at the desktop, laptop, workstation, and mobile markets.

Skills

Required

  • Physical Design
  • RTL2GDSII flow
  • Synthesis
  • Place & Route
  • CTS
  • Timing convergence
  • Layout closure
  • High frequency design
  • Block-level Floor-planning
  • Full-chip Floor-planning
  • Physical verification
  • ICC2/Innovus
  • Primetime/Tempus
  • Timing constraints
  • STA
  • PERL
  • TCL
  • Scripting

Nice to have

  • Synopsys
  • Cadence
  • Make scripting

What the JD emphasized

  • 4+ years of experience in Physical Design
  • Strong understanding in the RTL2GDSII flow or design implementation in leading process technologies
  • Good understanding of the RTL2GDSII concepts related to synthesis, place & route, CTS, timing convergence, layout closure
  • Expertise on high frequency design methodologies
  • Good knowledge and experience in Block-level and Full-chip Floor-planning and Physical verification
  • Working experience with tools like ICC2/Innovus, Primetime/Tempus etc used in the RTL2GDSII implementation
  • Strong knowledge and experience in standard place and route flows ICC2/Synopsys and Innovus/Cadence flows preferred
  • Well versed with timing constraints, STA and timing closure
  • Good automation skills in PERL, TCL, tool specific scripting on one of the industry leading Place & Route tools