Job Details:
Job Description:
The Role and Impact: As a Physical Design Engineer, you will play a pivotal role in transforming innovative ideas into manufacturable products, contributing directly to Intel's success in delivering cutting-edge solutions. This position involves implementing custom IP and System-on-Chip (SoC) designs from RTL to GDS, ensuring high-quality design databases are ready for manufacturing. Your work will optimize key product parameters such as power, frequency, and area, enabling Intel to maintain its leadership in the semiconductor industry. By leveraging your expertise, you will contribute to shaping future product architectures and advancing physical design methodologies, reinforcing Intel's commitment to innovation and excellence. Key Responsibilities: - Execute physical design implementation of custom IP and SoC designs, taking them from RTL to GDS for manufacturing-readiness. - Conduct all aspects of the physical design flow, including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, and noise analysis. - Perform verification and signoff processes, such as formal equivalence verification, reliability verification, and layout verification, ensuring compliance with electrical rules and design standards. - Analyze results to identify and resolve violations, providing recommendations to improve current and future product architectures. - Optimize designs to achieve desired power, frequency, and area targets while balancing product-level requirements. - Participate in the development and automation of physical design methodologies and workflows to increase efficiency and scalability. - Collaborate with cross-functional teams to address complex design challenges and contribute to the continuous improvement of Intel's products and processes.
Qualifications:
Minimum Qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related specialized field.
- 10+ years of experience in physical design implementation with a Bachelor's degree, 8+ years with a Master's degree, or 6+ years with a PhD.
- Proficiency in industry-standard EDA tools for synthesis, place and route, timing analysis, formal verification, and design closure.
- Expertise in scripting languages such as Python, Perl, and TCL for design flow automation and optimization.
- Solid understanding of RTL-to-GDS (Graphic Design System) methodologies and workflows.
- Knowledge of power integrity, clock distribution, reliability verification, and DFT techniques.
Preferred Qualifications:
- Strong analytical and problem-solving skills with a disciplined approach to execution.
- Experience with low-power design techniques, including UPF implementation and verification.
- Familiarity with system and processor architectures, and their interactions with software.
- In-depth knowledge of industry standard IPs like ARM designs.
- Exposure to formal verification and hardware validation techniques.
- Proven ability to collaborate effectively with teams, driving innovative solutions and continuous process improvements.
Join Intel today to shape the future of technology and make a lasting impact in the world of semiconductor design.
Job Type:
Experienced Hire
Shift:
Shift 1 (Malaysia)
Primary Location:
Malaysia, Penang
Additional Locations:
Business group:
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
- ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.