Senior Physical Design Engineer

NVIDIA NVIDIA · Semiconductors · Westford, MA

Senior Physical Design Engineer for NVIDIA's Networking Silicon engineering team, focusing on the physical design and implementation of SOC devices for networking markets. Responsibilities include chip floorplan, power/clock distribution, P&R, timing closure, and physical verification, working with advanced process nodes (5nm, 4nm, 3nm).

What you'd actually do

  1. You will lead all aspects of physical design and implementation of SOC devices targeted at the networking markets.
  2. Work will be at the partition and chiplet level.
  3. As a member of a team, you will participate in establishing physical design methodologies, flow automation, chip floorplan, power/clock distribution, chip assembly and P&R, timing closure.
  4. Daily work involves all aspects of physical chip development (RTL2GDS) – trial synthesis, power and clock distribution, place and route, timing closure, power and noise analysis and physical verification.

Skills

Required

  • BSEE / MSEE or equivalent experience
  • 5 years of experience in VLSI physical design implementation on 5nm, 4nm and 3nm technology
  • VLSI physical design implementation
  • P&R
  • Timing Analysis
  • Physical Verification
  • IR Drop Analysis
  • Synopsys (ICC2/DC/PT/STAR/ICV)
  • Cadence (Genus/Innovus/Tempus)
  • timing closure
  • clock/power distribution and analysis
  • RC extraction and correlation
  • place/ route and tapeout solutions
  • strong analytical and debugging skills

Nice to have

  • Python
  • Perl
  • Tcl
  • Make scripting

What the JD emphasized

  • A successful track record of delivering designs to production is a requirement.
  • Able to assist in design flow development and debugging, including application of ML/AI solutions.