Senior Physical Design Engineer

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA +1

NVIDIA is seeking a Senior Physical Design Engineer to be responsible for the physical design and implementation of GPUs and other ASICs. This role involves establishing design methodologies, chip floorplan, power/clock distribution, assembly, P&R, and timing closure. The engineer will also craft designs for static timing analysis, power/noise analysis, and back-end verification, working with advanced process nodes (5nm, 4nm, 3nm) and various CAD tools.

What you'd actually do

  1. Responsible for all aspects of physical design and implementation of GPU and other ASICs targeted at the desktop, laptop, workstation, and mobile markets.
  2. As a member of a team, we will all participate in establishing physical design methodologies, flow automation, chip floorplan, power/clock distribution, chip assembly and P&R, timing closure.
  3. Craft designs for static timing analysis, power and noise analysis and back-end verification.

Skills

Required

  • BSEE (MSEE preferred) or equivalent experience
  • 5 years of experience in large VLSI physical design implementation on 5nm, 4nm and 3nm technology
  • successful track record of delivering designs to production
  • Power, Performance and Area improvement Initiatives
  • P&R, Timing analysis, Physical Verification and IR Drop Analysis CAD tools from Synopsys (ICC2/DC/PT/STAR-RC/ICV),Cadence (Innovus, Tempus, SeaHawk ) and Mentor Graphics
  • Deep understanding of custom macro blocks such as RAMs, CAMs, high-speed IO drivers, PLLs
  • Confirmed prior experience in timing closure, clock/power distribution and analysis, RC extraction and correlation, place/ route and tapeout solutions
  • strong analytical and debugging skills

Nice to have

  • Python, Perl, Tcl, Make scripting

What the JD emphasized

  • successful track record of delivering designs to production is a requirement